The present invention is based on Korean Patent Application No. 10170/1995 filed on Apr. 27, 1995, which is explicitly incorporated herein by reference.
1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to the formation of transmission lines in parallel buses within semiconductor memory devices which results in reduced skew between the signals transmitted on the various lines of the parallel bus. The reduced skew enables higher speed operation than would otherwise be possible.
2. Description of the Related Art
The speed of operation is very important in semiconductor memory devices, particularly when combined with other advantageous features such as high integration and low power consumption. However, skew is often a limiting factor in the limit to which speed can be increased. Skew occurs between the various lines of a parallel data bus in large part because of the difference in length and other characteristics between each individual transmission line within the semiconductor device. It is very desirable to reduce the skew so that the bandwidth of the semiconductor device is increased. However, since it is impossible in practice to place all internal circuits comprised in the semiconductor memory device in locations which would make all transmission lines of a parallel bus equal in length, width and other characteristics, mostly due to the limited chip size and desire to provide higher integration in semiconductor memory devices, it is very difficult in practice to reduce the skew beyond certain conventional levels.
FIG. 1 is a diagram showing a conventional arrangement of representative internal circuits connected to a parallel bus in a semiconductor memory device. The configuration and operation of the conventional semiconductor memory device will now be described with reference to FIG. 1.
In systems using parallel buses, e.g., microprocessor-based systems, various parallel control signals are input into a semiconductor memory device through pads (not shown) so as to drive storage elements, e.g., memory. In the conventional device as shown in FIG. 1, external parallel control signals are input into the semiconductor memory device through the pads. These parallel control signals are then typically buffered by passing them through a parallel bank of buffers within the chip, and then become internal parallel control signals IN1 to IN8 as shown in FIG. 1. The internal parallel control signals IN1 to IN8 are applied to a first parallel bank of internal circuits 12a-12h forming a first circuit unit. The signals output from the first parallel bank of internal circuits 12a-12h are then transmitted over a parallel bus formed of individual transmission lines 16a-16h, and received by a second parallel bank of internal circuits 14a-14h comprised in a first circuit unit, which then outputs respective parallel output signals OUT1 to OUT8.
The sensing signal S1 is transmitted on line 20 to enable the second parallel bank of internal circuits 14a to 14h comprised in the second circuit unit. The use of sensing signals is well known in the art and thus only a brief description is given herein.
FIG. 2 is an operational timing diagram of FIG. 1. As can be seen from FIG. 2, a time lag t1 occurs between the output of the fastest one of the parallel output signals OUT1 to OUT8 and the slowest one of the parallel output signals OUT1 to OUTS. This is due to a skew in the arrival time of the individual lines of the parallel control signals. Thus, the transmission time of signals on the individual transmission lines 16a-16h is not identical but rather varies between the respective first parallel bank of internal circuits 12a to 12h and the second parallel bank of internal circuits 14a to 14h. This time interval makes the respective output times from the second parallel bank of internal circuits 14a to 14h different from one another, thereby causing a time interval between the output signals OUT1 to OUT8. It will be understood and appreciated by those skilled in the art that the longer this time interval due to skew between the individual transmission lines 16a to 16h, the slower the device becomes because the device is only as fast as the slowest transmission line 16a to 16h. Thus, the skew makes high speed operation difficult.
Another conventional technique for reducing skew is to vary the size of internal driving circuits such that skew is reduced. However, this technique proves to be a complicated solution to reduce skew.